1. Field of the Invention
The present invention relates to a semiconductor testing device, and particularly to a semiconductor testing device for testing a semiconductor device using redundant circuits.
2. Description of the Related Art
In a conventional semiconductor testing device, a laser beam is irradiated onto a semiconductor device to test the semiconductor device by scattered light or pattern comparison or the like, and if any defective (e.g., defect chip) is detected through the testing, the quality of the device is judged on the basis of the number of defectives (defects chips).
However, when a semiconductor device having redundant circuits is tested, it is necessary that defects which can be relieved by the redundant circuits and defects which cannot be relieved by the redundant circuits are discriminated from one another and then the test result is considered on the basis of the discrimination.
A testing method for a semiconductor device having redundant circuits is disclosed in Japanese Laid-open patent Application No. Hei-7-142547. FIG. 4 is a diagram showing a testing method of a semiconductor testing device disclosed in Japanese Laid-open Patent Application No. Hei-7-142547.
As shown in FIG. 4, according to the conventional semiconductor device testing device, chips on the same device are visually inspected to find out defective chips in each of manufacturing processes A, B and C, and the chip coordinates of the defective chips are collected (step S21). The number of type-basis replacement usage of redundant circuits in each manufacturing process, which is obtained by replacing the redundant circuits for a defective chip, is determined (step S22). As a result of the visual inspection of all the manufacturing processes on the same device, the type-basis replacement usage number of the redundant circuits is accumulated for every same device to calculate the accumulated value of the redundant circuits on a type basis (step S23). The defectiveness or non-defectiveness is judged on the basis of a judgment as to whether the added accumulated value (total value) exceeds a preset limit value (step S24). If the accumulated value is judged to exceed at least one type-basis limit value, the testing of the chip concerned is omitted. If the accumulated value is judged not to exceed the limit value, the chip concerned is judged to be a non-defective chip which can be relieved by the redundant circuits, and thus the chip is transferred to a chip test process.
In a recent semiconductor device having redundant circuits, in most cases, not only the total usage number is determined, but also the usage number is determined in every area of a chip. Accordingly, it is necessary to make a judgment as to whether the defect (e.g., chip) is relievable or irrelievable in consideration of the device information.
However, in the prior art as described above, the usage number of redundant circuits is determined every same device, and it is judged on the basis of the usage number whether the defect of the device is relievable or irrelievable. Therefore, the prior art has a problem that the yield cannot be accurately estimated.